In synchronous designs, a peak in the supply current occurs right after the clock edge. As power density increases, power network parasitics together with faster switching times and lower noise margins cause an increasing sensitivity to dynamic voltage (IR) drops. Local IR drop peaks can be fixed with decoupling capacitance, however this solution has a cost in terms of increased leakage current. Furthermore, in scaling technologies the total filler area to use for inserting local decoupling is also decreasing. Hence this solution is merely postponing the problems.
Using the FloorDirector's automated, power-driven floorplanning, it is possible to shape the power signature at the system level, hence reducing both current peaks and digital noise. It is thus possible for designers to limit the necessity for decoupling capacitance and reduce the power pad count.
