In synchronous designs, a peak in the supply current occurs right after the clock edge. As power density increases, power network parasitics together with faster switching times and lower noise margins cause an increasing sensitivity to dynamic voltage (IR) drops and power grid noise. Local IR Drop peaks can be patched with decoupling capacitance, however this solution has a cost in terms of increased leakage current. Furthermore, in scaling technologies the total filler area to use for inserting local decoupling is also decreasing. Hence this solution is merely postponing the problems.
Using the FloorDirector's automated, Dynamic Power Shaping option, it is possible to shape the current signature at the system level, hence reducing both IR Drop peaks and digital noise. This fans out to a range of benefits such as reduced decoupling capacitance, improved noise margins, improved analog performance, enhanced EMI/EMC, and more.
- Real world example of dynamic supply current analysis and optimization: System-level current peak reductions by FloorDirector show the efficiency of the algorithms and optimization engine. All reductions are achieved while maintaining existing timing margins. Click on picture to enlarge.
