As IC fabrication technologies scale into nanometer geometries, parametric process variations add to SoC design uncertainty. The requirement to design robust systems prevails. Due to large chip sizes, modular design approaches, increasing variability and geometry scaling, timing and power closure presents a major bottleneck in the design process. To help IC design companies reduce development costs, higher levels of automation for hierarchical design and better handling of on-chip variability and power density issues are needed.
The FloorDirector™ is a software tool developed at Teklatech, which handles floorplanning and system-level clock distribution issues in nanoscale geometries. The technology addresses key challenges in designing advanced SoCs.
