FloorDirector
Complex System-on-Chip (SoC) designs at deep submicron geometries suffer from increasing power grid noise and IR Drop due to dynamic supply currents with high peaks and steep slopes. Particularly ICs for highly integrated portable and automotive applications, as well as RF and mixed-signal ICs with noise-sensitive analog blocks, are suffering the drawbacks of technology scaling. Furthermore, higher power density and reduced supply voltages make IR Drop increasingly challenging in both wire-bond and flip-chip designs. Today, dynamic digital power issues present a major obstacle in achieving design closure within the design schedule and budget.
- Dynamic supply current analysis and optimization: System-level current peak reductions by FloorDirector show the efficiency of the algorithms in a real-life design. All reductions are achieved while maintaining existing timing margins. Click on picture to enlarge.
FloorDirector provides an ASIC design solution which enables early stage chip-level dynamic power analysis and implementation-phase optimization, allowing your backend design team to reduce system-level current peaks, dynamic IR Drop and digital power grid noise in SoC designs.
FloorDirector works on a post-synthesis netlist, and hence optimizations are done in the early stages of your backend design flow. This provides designers with a comprehensive system-oriented solution to address the complexity of SoC digital noise and power integrity before physical implementation. As the optimization is performed at the logic design level before detailed layout, design improvements are complementary to improvements made during physical implementation. And, as FloorDirector plugs seamlessly into the flow at a very early stage design iterations vary short and fast. Click on picture to enlarge
In summary, FloorDirector offers multiple benefits:
- Reducing dynamic IR Drop and system-level current peaks to improve noise margins
- Reducing digital noise already in the implementation phase
- Enhancing EMC/EMI performance by noise frequency domain analysis
- Improving analog performance by minimizing substrate coupled noise
If you would like to know more, please submit your contact information and a Teklatech representative will contact you with more information. Thank you for your interest in our products.
