Improving Power, Yield and Time-to-Market

FloorDirector™ is a clock- and floorplanning tool which enables ASIC designers to reduce IR drop and noise in system-on-chip designs by flattening dynamic power peaks through automated floorplanning and clock scheduling techniques.

The tool combines a full timing engine and advanced dynamic power analysis into a fully automated optimization engine which performs system-level power shaping to reduce critical power peaks.

Optimization from fixed, predefined floorplans are also possible by advanced power shaping capabilities. 

 

Figure 1: FloorDirector address physical level issues at early design cycle

Product overview

  • Power-aware floor-planning and clock-scheduling 
  • Detailed system-level power analysis 
  • Solving dynamic IR drop and noise issues 
  • Addressing physical level issues at early stage‏ 
  • Scalable with technology scaling 
  • Complimentary tool - integrates into existing flows
Figure 2: FloorDirector - IR Drop Aware FloorPlanning

Power Analysis Features

FloorDirector offers a power analysis environment for early estimation of block and chip level power signatures. The power analysis allows tracking and identifying all power peaks and block to block power dependencies.  

- Block Level

  • Dynamic power signature analysis 
  • Block exploration (split/merge blocks) 
  • Block-to-block comparison 
  • Impact of block behavior on entire chip

- Chip Level 

  • Full-chip peak power analysis 
  • Insight into block to block power dependencies 
  • Identify high potential clock gating points 
  • Floorplan and power pads guidance
Figure 3: Power Signatures of 4 SoC’s blocks (worst-case)

Floorplanning Engine

  • IR drop and current slope driven optimization 
  • Data Flow awareness 
  • Maintaining global timing margins 
  • Shaping chip's power signature 
  • Solving dynamic IR drop and noise issues
Figure 4: FloorDirector - Power Peak Reduction

Summary

  • Reduce power peaks
  • Reduce dynamic voltage drops 
  • Improve noise margin 
  • Allow lower Vdd – save power 
  • Reduce decoupling capacitors 
  • Improved EMI and RFI
  • Reduce power/gnd pad count 
  • Increase yield 
  • Scalable solution

Request Datasheet

If you would like to request product collateral please submit your contact information and a Teklatech representative will e-mail you a data sheet. Thank you for your interest in our products.

Full Name
 Phone number
Company name
 E-mail
 
 Request Datasheet about FloorDirector