Teklatech - wiring up your SoC™
A technology visionary and industry pioneer, Teklatech provides targeted EDA solutions for advanced system-on-chip design. With innovations in floorplanning and clock distribution networks Teklatech is focused on meeting the stringent demands of next-generation semiconductor industry.
Power Shaping
With increased power density, wire parasitics and signal transients, dynamic IR drops and mixed-signal noise coupling degrades both digital and analog noise margins.
By advanced clock distribution and floorplanning methods, the FloorDirector™ actively shapes the power signature of SoC designs. Dynamic voltage drop peaks and coupling noise can be reduced without the need for leaky decoupling capacitances.
Cycle Stretching
Pushing designs across to target is a real challenge. A traditional, fixed-phase clocking scheme does not leave much slack for optimizing design margins.
In order to get the most out of a given technology, the FloorDirector™ allows controlled use of beneficial clock skew. This can be used to push a design across to performance target, keeping it on the right side of the performance-cost curve sweet spot.
OCV Robustness
To help IC design companies reduce development costs, higher levels of automation for hierarchical design and better handling of on-chip variability are needed.
The FloorDirector™ addresses clock distribution under increasing on-chip variability. The tool enables a scalable and variability robust method for top-level SoC clock distribution, realizing a bounded local skew for any size system.
